In the quest for higher processing power, various hardware architectures have been proposed, including digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) and general CPUs. As might be expected, however, even the fastest processors are not fast enough for the newest real-time applications that are conceived by system designers. Typically, any algorithm used is optimized to take into account the characteristics of the particular hardware/software implementation. A typical optimization method is to not use available information to its fullest, thus conserving computing time and remaining within the limits of the hardware capabilities, trading off performance for quality.
Cellular telephone systems are well known. One of the new system concepts is the UMTS (Universal Mobile Telecommunication System) architecture, also known as the 3G architecture. The current suggested standards are 3GPP1, for UMTS and 3GPP2 for a different concept known as CDMA2000. Both concepts define various protocols for implementing high data rate digital communications using a WBCDMA (Wide Band Code Division Multiplexing Access) method.
A considerable amount of signal processing is required to implement the algorithms defined by the suggested standards, especially in the base station where signals from multiple users, all broadcasting at the same time and frequency, must be detected and analyzed. The standard solution is to optimize the algorithms, for execution on DSPs or ASICs. However, even after such optimization, available processing power is not sufficient for the task and many of the protocols are not implemented in a complete manner (e.g., ignoring some available information and trading off performance for quality) or, alternatively the protocols are implemented on a multi-card device, with the users distributed between multiple costly cards.
A processor architecture referred to as “Stanford optical VMM”, described for example in Dror G. Fietelson, “Optical Computing”, Chapter 4.3, MIT press 1988, the disclosure of which is incorporated herein by reference, suggests performing vector matrix multiplication (VMM) using an optical model based on a transparency matrix. An analog electronic vector-matrix multiplication unit is described, for example, in “Programmable Analog Vector-Matrix Multipliers”, by F. Kub, K. Moon, I. Mack, F. Long, in IEEE Journal of Solid-State Circuits, vol. 25 (1) pp. 207-214, 1990, which is incorporated herein by reference.
U.S. Pat. Nos. 4,937,776, 5,448,749 and 5,321,639 apparently describe architectures including optical components, which are suggested for use for matrix/vector manipulation.